1. Field of the Invention
The present invention relates generally to a method and apparatus for testing a semiconductor memory device. The present invention also related to a semiconductor memory device adapted to testing in a reduced testing time.
A claim to priority is made to Korean Patent Application No. 2003-88677 filed on Dec. 8, 2003, the subject matter of which is incorporated by reference.
2. Description of the Related Art
The typical apparatus for testing a semiconductor memory device incorporates several different methods to test for various failures in the device. One test method commonly run is the parallel bit test (PBT). The PBT tests a plurality of memory cells using only a small number of data pins. A conventional semiconductor memory device typically includes an even number of memory cells on every column, and an even number of data pins. Thus, conventional methods for testing such a semiconductor memory device expect to see a plurality of memory cells having an even number of data pins.
However, these conventional test methods cannot be applied to a network of Dynamic Random Access Memory (DRAM) because the DRAM typically include at least some memory cells storing parity information. As a result, the apparatus conventionally used to test a semiconductor memory device included in a network of DRAM require additional data pins, and generally use an odd number of data pins.
Additionally, the time required to test conventional semiconductor memory devices tends to rise as the number of data pins on the devices increases. Given the trend towards higher pin counts, the duration of certain test times is becoming an issue. In sum, the conventional apparatuses and methods applied to the testing of semiconductor memory devices result in unacceptably long test times. Test times must be further reduced without increasing or otherwise altering the then number of data pins associated with the semiconductor memory devices.